The present invention relates to an information processor, and more particularly to a processing system having a function to correct, revise or rectify information stored in a memory.
Information processors which carry out commands or instructions given by program operation or key manipulation are widely used in many fields, today. They have also come to be used in systems to display character or graphic patterns as large capacity, low cost memories were placed on market. For instance, the pattern data to be displayed on a raster-scan type cathode ray tube (hereinafter referred to as "CRT") are prepared by a data processor. In this case, the display pattern data are stored in the memory as a group of bit information. Here, one bit information corresponds to one picture element data of a CRT. The required bits of information are sequentially read out and transferred one by one to the display by addressing the memory. For this purpose, the data processor has addressing means which is capable of designating the required bit information. If the screen of a CRT is organized of, for example, 1024.times.1024 picture elements, the memory should have a capacity of 1024.times.1024 bits (about 1 mega bits).
On the other hand, the pattern is changed sequentially by changing the previous bit information stored in the memory, to be newly displayed on the screen. Thus, a data processor is required to have a function to change, bit by bit, the previous bit information according to the program.
The bit changing means in the prior art used a word addressing system which reads out simultaneously a plurality of bit data for one addressing. By first reading the word data (pattern data) of plural bits (i.e. of 8 bits, 16 bits, 32 bits, etc.) from the memory, the similar changing was performed in respect of all the bits of the word data thus read out. Thereafter, a specific memory cell corresponding to the bit location to be changed was designated by bit addressing means, and the bit data which had been changed was written therein one by one. At that writing time, the bit addressing means was used for selecting the specified memory cell. It then became possible to change the specific one bit of the word data.
However, this conventional means required the one memory cell selection for storing the changed bit data, which in turn required a complex circuit for bit addressing means. This bit addressing circuit, moreover, had to be connected separately for each of the memory elements in which the word data was written. This form of addressing necessarily complicated wiring between the bit addressing circuit and the memory elements. Further, such an addressing application was unsuitable for larger capacity memories, because of restrictions upon the number of memory elements capable of selection by the bit addressing means. Thus, it was impossible to install more memory elements.
The prior art information processor had an additional drawback that changed bit data were stored one by one in the specified memory location, at a different timing, thus prolonging the time required for storing the newly displayed pattern data in the memory. This redundancy of the changing time exerted undesirable effects on the CRT display.